1. Field of the Invention
The invention relates to a method for polishing a semiconductor wafer by means of chemical mechanical polishing (CMP).
2. Background Art
CMP is a single-side polishing that is usually used to reduce the roughness of the front side of a semiconductor wafer. It is therefore also referred to as mirror polishing. During CMP, the semiconductor wafer is pressed on the side to be polished against a rotating polishing cloth by a rotating polishing head and is smoothed in the presence of a polishing agent supplied. The material removal brought about during polishing depends, inter alia, on the pressure with which the semiconductor wafer is pressed against the polishing cloth. There is also the possibility of choosing the polishing pressure to be different in different zones, thereby bringing about a material removal which leads to a nonuniform profile when the material removal is viewed along the diameter of the semiconductor wafer. Pressure zones can be established for example with the aid of pressure chambers or pressure rings. A polishing head having a carrier which enables a subdivision into pressure zones is described for example in U.S. Pat. No. 5,916,016. The CMP can accordingly also be used to influence the geometry of the semiconductor wafer in a targeted manner, that is to say the parameters of the semiconductor wafer which describe the local and global flatness.
Alongside CMP, DSP (“double side polishing”) plays an important part in the polishing of semiconductor wafers. DSP involves generally a plurality of semiconductor wafers being polished simultaneously. During the DSP, a semiconductor wafer lies between two polishing plates provided with polishing cloth in a cutout of a carrier and is polished on both sides with the aid of a polishing agent supplied. DSP has the task, in particular, of eliminating damage in the region of the surface that has remained after shaping mechanical machining by lapping and/or grinding of the semiconductor wafer. The material removal is significantly higher in the case of DSP, usually having total removal of 10 to 30 μm more than that in the case of CMP. Therefore, DSP is often also referred to as stock removal polishing.
Standardized parameters are available for the quantitative characterization of the geometry of semiconductor wafers. This also applies to the edge region of the front side of the semiconductor wafer, where the front side is usually taken to mean that side of a semiconductor wafer which is used as a basis for the integration of electronic components.
The manufacturers of electronic components also endeavor to include the edge region as comprehensively as possible in the usable area FQA (“Fixed Quality Area”). Accordingly, the specified permitted edge exclusion EE is becoming ever smaller. At the present time demanding specifications permit only an edge exclusion of 1 mm.
Unevennesses can be described by the parameter SFQR. SFQR denotes the local flatness in a measurement zone having a specific dimensioning, for example an area of 20 mm×20 mm, to be precise, in the form of the maximum height deviation of the front side of the semiconductor wafer in the measurement zone with respect to a reference area having the same dimensioning that is obtained by error square minimization. Partial sites are measurement zones in the edge region which are no longer fully part of the FQA, but the center of which still lies in the FQA. The parameter PSFQR denotes the local flatness in partial sites, as does the parameter ESFQR. The latter is based on a more comprehensive metric.
Alongside the local flatness, it is always necessary to also take into account the global flatness of the front side of the semiconductor wafer. Standardized parameters for describing the global flatness are GBIR and SBIR, which correlate with this value. Both parameters express the maximum height deviation of the front side relative to a rear side—assumed to be ideally flat—of the semiconductor wafer and differ in that the FQA is used for calculation in the case of GBIR and the area restricted to a measurement zone is used for calculation in the case of SBIR.
Definitions of the abovementioned parameters and descriptions of methods for measuring said parameters are contained in the relevant SEMI standards, in particular in the M1, M67 and M1530 standards.
The thickness of a semiconductor wafer polished by means of DSP usually decreases significantly toward the edge. This edge roll-off can impair the global flatness and the local flatness in partial sites. It is desirable, therefore, to limit the edge roll-off as far as possible to the region of the edge exclusion.
US2003/0022495 A1 proposes, for reducing the edge roll-off, firstly polishing the rear side of the semiconductor wafer in such a way that a reference plane arises. For this purpose, the front side is sucked against a stiff carrier and a material removal amounting to preferably 3 to 8 μm is brought about on the rear side. Afterward, the front side of the semiconductor wafer is polished.